Method and apparatus for display image rotation

ABSTRACT

A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set of CPU addresses, a memory for storing the frame buffer, a controller for directing the pixel data of the frame buffer to a display device using a set of controller addresses. The two sets of addresses are not necessarily the same. In fact, numerous advantages could be had from manipulating those two sets of addresses resulting in image rotation operations for the display device.

FIELD OF THE INVENTION

This invention relates generally to a processor-controlled system suchas a computer system and, more particularly, but not exclusively, to anelectrical arrangement in the system for managing video information forrotating computer display images.

BACKGROUND INFORMATION

Among the many image resolutions for computer displays in the markettoday, a common resolution for computer displays is 640×480. Suchresolution for a display refers to a display having an overall screenmeasuring 640 pixels wide by 480 lines high. In fact, any displayshaving this horizontal format (i.e., its width being greater than itsheight) would provide ease and convenience for certain computeroperations including showing TV images, operating drawing programs andperforming spreadsheet calculations. Nevertheless, displays with avertical format (i.e., its height being greater than its width) arebetter suited for certain other operations such as word processing,program coding and Internet access. One may suggest a computer displayhaving a square viewing area (i.e., equal height and width) forsatisfying both requirements, but practically speaking, the most commoncomputer displays today are rectangular, and that forces an user tochoose either a horizontally or a vertically formatted display at thetime of purchase.

It would be ideal if a display device could rotate between thehorizontal format and the vertical format depending on user needs andpreference. While this rotation feature is useful for operating numerouscomputer applications, it is especially advantageous for pen-based andhand-held computers where the user's ability to comfortably operate thecomputer is greatly affected by the orientation and position in whichthe computer is held.

One known implementation discloses a computer system having a displaydevice which can be physically rotated along its sides 90 degrees ineither of two directions. Such a system can then cause the displaydevice to display its image contents correctly adjusted for thenewly-rotated display orientation. Unfortunately, typical imageorientation adjustments for the rotated display monitor have significantperformance penalty associated with their necessarycalculation-intensive axis transformations.

SUMMARY OF THE INVENTION

It would be desirable and therefore an object for the present inventionto provide a method and apparatus for rotating computer display images90 degrees on a display device with little or no transformationcalculations. It is another object for the present invention to providethe image rotation for the display device in both clockwise andcounter-clockwise directions to support both left-handed andright-handed users. Yet another object for the present invention is toimplement such rotation feature without significant system performancepenalty.

Additional objects and advantages of the present invention will be setforth in the description which follows, and in part, will be obviousfrom the description or may be learned by practice of the invention. Toachieve the foregoing objects, and in accordance with the purpose of theinvention as embodied and broadly described herein, briefly, there isprovided an apparatus including a memory system containing an imageframe buffer for an associated display device, this memory system beingcoupled to a CPU and also being coupled to the display device via itsvideo display controller. The image frame buffer can be manipulated bythe CPU and retrieved by the video display controller for use by thedisplay device. One aspect of the invention discloses an implementationwherein the CPU addresses the image frame buffer in a manneradvantageous for CPU manipulation and the video display controlleraddresses the same image frame buffer in another manner advantageous forframe buffer retrieval by the video display controller. Such retrievalincludes image presentations on the display device in a vertical formatas well as in a horizontal format depending on user selection. Duringimage rotation, one preferred but not limiting aspect of the inventionprovides the memory system, under the control of the video displaycontroller, physically storing the image frame buffer in memorylocations which are different from the locations as addressed by theCPU. Although typical display image rotation can be accomplishedentirely in software, another aspect of the present invention providesan implementation that is operable entirely in hardware.

The present invention also may take advantage of the fact that the imageframe buffer in the memory system is typically defined as a series ofbytes storing the image information for the first horizontal line of thedisplay device, followed by a fixed gap of unused bytes, and followed byanother series of bytes for the next horizontal line of the displaydevice, then another gap of unused bytes, and so on. For a displaydevice measuring h pixels wide, by v pixels high, this makes an imageframe buffer of v lines, each line containing the number of bytes neededto store the image data for h pixels plus a fixed number of unused gapbytes. The image frame buffer implemented as described provides furtheradvantages for image rotation, if two other conditions are met: 1. A“defined frame buffer” (which contains the portion of the frame bufferused for the actual display data) starts at a page boundary addresswhere all the address bits needed to describe offsets within the definedframe buffer are 0 (for a 1 megabyte buffer, for example, this means theleast significant 20 bits of the lowest defined buffer address should be0, a condition met by an hexadecimal address ending in 00000); and 2.The sum of the number of image data bytes per display line plus thenumber of gap bytes per line is a power of 2 (such as 2¹⁰=1024 bytes).

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part ofthis specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention:

FIG. 1 is a schematic diagram illustrating a partial computer systemincluding a preferred embodiment of the present invention for rotatingdisplay images on a display device;

FIG. 2 illustrates how a “defined frame buffer” containing an alphabet“F” in the vertical format is “viewed” or addressable by the CPU;

FIG. 3A illustrates an addressing scheme used by the CPU of the partialcomputer system of FIG. 1 for accessing frame buffer information;

FIG. 3B provides a table illustrating a number of the frame bufferaddressing parameters for several typical display resolutions currentlyavailable;

FIG. 4 illustrates an embodiment of the present invention for CPUaddress transformation either in hardware or in software for providing arotated image having a different orientation on a display device thanthat of the original image;

FIG. 5 illustrates a resulting image after the row and column addressesfor the image shown in FIG. 2 have been exchanged in accordance with thepresent invention;

FIG. 6 illustrates a counter-clockwise 90° rotation of the image asshown in FIG. 2 implemented by an embodiment of the present invention;

FIG. 7 illustrates a clockwise 90° rotation of the image as shown inFIG. 2 implemented by an embodiment of the present invention;

FIG. 8A illustrates a CPU address transformation embodiment either inhardware or in software for providing a 90° counter-clockwise imagerotation for images on a display device;

FIG. 8B illustrates a CPU address transformation embodiment either inhardware or in software for providing a 90° clockwise image rotation forimages on a display device;

FIG. 9A illustrates a rotated image as stored in the frame buffer memoryin the embodiment illustrated in FIG. 8A;

FIG. 9B illustrates an image appearance on the display device aftercounter-clockwise image rotation operation for the embodimentillustrated in FIG. 8A;

FIG. 10A illustrates a rotated image as sorted in the frame buffermemory in the embodiment illustrated in FIG. 8B; and

FIG. 10B illustrates an image appearance on the display device after aclockwise rotation image operation for the embodiment illustrated inFIG. 8B.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to preferred embodiments of theinvention. While the invention will be described in conjunction with thepreferred embodiments, it should be understood that they are notintended to limit the invention to these embodiments. On the contrary,the invention is intended to cover alternatives, modifications, andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims.

Throughout this detailed description numerous details are set forth inorder to provide a thorough understanding of the present invention, forexample, multiple references are made to specific computer displayresolutions and data word bit-widths of communication lines. Thesespecific values are exemplary only. To one skilled in the art, however,it will be appreciated that the present invention may be practicedwithout such specific details and that a wide range of displayresolutions and data-word-bit-width values can be used within the scopeof the present invention. In other instances, well-known methods,procedures, control structures and gate level circuits have not beenshown in detail in order not to obscure the present invention.

With today's device technology, the development of specializedintegrated circuits and programmable logic generally do not require therendering of fully detailed circuit diagrams. The definition of logicfunctionality allows computer design techniques to design the desiredlogic and circuits. Additionally, microcontrollers are known to operatebased on a desired flow diagram rendered into software that iscompatible with a selected microcontroller. Accordingly, portions of thepresent invention will be described primarily in terms of functionalityto be implemented by a microcontroller and other associated electroniccomponents. This functionality will be described and those of ordinaryskill in the art, once given the following descriptions of the variousfunctions to be carried out by the present invention will be able toimplement the necessary microcontroller structure and logic for variouslogic devices or custom designed integrated circuits in suitabletechnologies without undue experimentation.

FIG. 1 is a block diagram illustrating a partial computer system 100 inaccordance with the present invention. This computer system 100 fortransferring information from one subsystem to another comprises asystem bus 110, an I/O bus 120, a memory bus 130, a frame buffer bus 140and a display bus 150. The computer system 100 further includes amicroprocessor (CPU) 155 being coupled to the system bus 110 forprocessing information and instructions, a system memory 165 beingcoupled to the memory bus 130 for storing information for system use, amemory controller/bridge 160 being coupled to the CPU 155 via the systembus 110 and to the system memory 165 via the memory bus 130, a framebuffer memory 170 being coupled to the frame buffer bus 140, a displaydevice 180 coupled to the display bus 150 and a graphics video displaycontroller 175 for processing image information and for directing theprocessed image information to the associated display device 180, thedisplay controller 175 being coupled to the frame buffer memory 170 andthe display device 180. The display device 180 may be a flat paneldisplay, a liquid crystal device, even a cathode ray tube device, orother display devices suitable for creating graphics images andalphanumeric characters recognizable to users. In fact, the displaydevice 180 is generic in that it could represent more than one display.Lastly, the computer system 100 includes other system I/O 185 such ashard disk, floppy disk and CD ROM subsystems.

In operation, an image frame buffer (not shown) to be displayed on thedisplay device 180 is stored into the frame buffer memory 170 by the CPU155. The graphics video display controller 175 may or may not interferewith the CPU 155 addressing of the image frame buffer inside the framebuffer memory 170. Presumably, such CPU addressing is advantageous forits operations. When the image shown on the display device 180 is to berotated, however, the graphics controller 175, at that time, willinterfere and manipulate the CPU 155 addressing of the image framebuffer without requiring the CPU 155 to spend its cycles on addresstransformation operations. Furthermore, the configuration of the framebuffer memory 170, graphics controller 175, and CPU 155 as shown in FIG.1 should not be construed as limiting in the sense that otherconfigurations can also be operable and be embodied within the scope ofthe present invention, for example, a configuration having a two-portedVRAM-like frame buffer memory where one port is coupled to a CPU and theother port is coupled to a graphics controller.

As discussed earlier in the Summary of the Invention that the concept ofa “defined frame buffer” would provide certain efficiency advantages forimage rotation. FIG. 2 illustrates how a defined frame buffer containingan alphabet “F” in the vertical format is “viewed” or addressable by theCPU 155. The defined frame buffer parameters H, V, x, and y and otherrelated parameters h, v, and b are briefly defined in FIG. 2. Inaddition, w is the width of the data bus to the frame buffer memory 170(i.e., the width of the frame buffer memory bus 140), and notnecessarily the width of the I/O bus 120. The horizontal width H of thedefined frame buffer (in bytes) is a power of 2 that equals or exceedsthe width h*b/8 of the display portion (also in bytes). Similarly, thevertical height V of the defined frame buffer (in lines) is a power of 2that equals or exceeds the number of vertical pixels v. For example, ifa vertical-format buffer is 600 pixels wide by 800 pixels high, at 16bits/pixel, the smallest value for H would be 2048 (i.e., the smallestpower of 2 larger than h*b/8=1200) and the smallest V would be 1024(i.e., smallest power of 2 larger than v=800). In general, to minimizethe amount of frame buffer memory 170 used, the value for H canpreferably be changed to a minimum value for each change in the value ofb, alternatively, H can be set permanently to a maximum valuecorresponding to the maximum value of b.

A frame buffer addressing scheme used by the CPU 155 in accordance withthe defined frame buffer concept is illustrated in FIG. 3A. The term“CPU address” refers to an address issued by the microprocessor (CPU)155 or another device when the executing software accesses the framebuffer. The graphics controller 175 accesses the frame buffer for imagedisplay and refresh using its own addresses (which may or may not be thesame as the CPU addresses). FIG. 3A shows a 32-bit address issued by theCPU 155 having row, column and byte address fields for accessing animage stored in the frame buffer memory 170. For implementationpurposes, the various field and defined frame buffer parameters for anumber of display resolutions, bits per pixel rates and frame buffermemory bus widths have been provided in FIG. 3B.

The graphics video display controller 175 can alter any CPU 155addresses received before actually writing or reading any imagesphysically stored in the frame buffer memory 170. As long as the samealteration is applied to both reading and writing operations, thesoftware will never know that the images are actually physically storedin a different format. In one preferred embodiment for image rotation,the graphics video display controller 175 creates a new, rotated framebuffer memory address by exchanging the CPU Column address bits with theCPU Row address bits as shown in FIG. 4. The CPU Byte address bitsretain their original position as the least-significant bits. If thisaddress transformation is used on both reads and writes by the CPU 155,then to the software, it will continue to “see” (address) anyre-oriented image frame buffer stored in the frame buffer memory 170 asin its original, and in this case, in its vertical, format. Forrefreshing the display images, however, the graphics controller 175 canread the image frame buffer as it is actually stored in its rotatedformat in the frame buffer memory 170. For example, one preferred aspectof the invention physically stores the image frame buffer as shown inFIG. 5 into the frame buffer memory 170. One does need to note that whatis actually stored into the frame buffer memory 170 depends on how andhow much of the present invention is implemented in hardware.

Applying the above transformations to one embodiment, the defined framebuffer shown in FIG. 2 as addressed by the CPU 155 is actually stored inthe frame buffer memory 170 as shown in FIG. 5. The CPU addresstransformation as illustrated in FIG. 4 is summarized in the following:

Rotated Row address bits=CPU Column address bits

Rotated Column address bits=CPU Row address bits

Rotated Byte address bits=CPU Byte address bits

This basic transformation has rotated software's vertical format to ahorizontal format, by simply exchanging the CPU columns for the CPU rows(lines). A closer look at the rotation reveals that it has been rotated90° counter-clockwise, but it is reversed vertically; in other words, itlooks like a mirror image of the original vertical frame buffer, androtated counter-clockwise. It does not provide the corresponding 90°image rotation desired when a display device or a hand-held computer isphysically rotated either clockwise or counter-clockwise. Nevertheless,such desired rotated images could still be obtained in a number of ways.

In another preferred embodiment, a correct, counter-clockwise 90° imagerotation for the image as shown in FIG. 2 can be derived from the imageas shown in FIG. 5 if the graphics controller 175 merely accesses therotated rows in the frame buffer memory 170 in reverse or decrementalorder when retrieving data for refresh, starting with the maximumrotated row (h*b/w)−1 and ending with row 0. The resulting rotated imageas displayed on the display device 180 is shown in FIG. 6.

Similarly, a clockwise 90° image rotation is obtained if the graphicscontroller 175 access the “rotated” columns in the frame buffer memory170 as shown in FIGS. 4 & 6 in the reverse or decremental order whenrefreshing the display, starting with the maximum rotated column v-1 andending with column 0. And the resulting image as displayed on thedisplay device 180 for a clockwise rotation is shown in FIG. 7.

It is not always convenient or possible to sequentially access the rowsor columns of a frame buffer in reverse order. For example, the graphicscontroller's DMA engine may be designed only for incremental displayrefresh operations. In response to this limitation, an implementationfor a 90° counter-clockwise rotation requires subtracting each rotatedrow address from the maximum rotated row address (H*8/w)−1 in thedefined frame buffer as shown in FIG. 5. This subtraction operation issimply accomplished by merely inverting each bit of the rotated rowaddress. The entire sequence of operations for this 90°counter-clockwise image rotation, i.e., an exchange of CPU row andcolumn addresses. Therefore, in this preferred embodiment, the CPUaddress transformation implementation is illustrated in FIG. 8A and thetransformed image and stored in the frame buffer memory 170 is shown inFIG. 9A. FIG. 9B illustrates the image appearance on the display device180 after a counter-clockwise rotation has been achieved by refreshingrotated rows H*8w-h*b/w to (H*8/w)−1 in an incremental order.Correspondingly, FIG. 8B illustrates a CPU address transformationimplementation for a 90° clockwise image rotation; briefly, it is anexchange of CPU column and bitwise-inverted row addresses. Thetransformed image stored in the frame buffer memory 170 for thisimplementation is shown in 10A. And FIG. 10B illustrates the imageappearance on the display device 180 after a clockwise rotation has beenachieved by refreshing rotated columns V-v to V-1 in an incrementalorder.

In either implementation, appropriate rotated images will be displayedwhen the graphics controller 175 retrieves data from the frame buffermemory 170 and refreshes the displayed images in a normal or incrementalmanner.

A variation to the above embodiment in which each row or column addressis subtracted from the maximum rotated row or column address in thedisplay portion of the defined frame buffer can be described as follows:

For 90° Counter-clockwise Image Rotation:

Rotated Row Address=Highest Display Column Address−CPU Column Address(note: Highest Display Column Address=[h*b/w]−1)

Rotated Column Address=CPU Row Address

Rotated Byte Address=CPU Byte Address

For 90° Clockwise Image Rotation:

Rotated Row Address=CPU Column Address

Rotated Column Address=Highest Display Row Address−CPU Row Address(note: Highest Display Row Address=v−1)

Rotated Byte=CPU Byte

This implementation is computationally more intensive than earlierembodiments; but it is perhaps conceptually more straightforward thanthe earlier embodiments. And it does allow the rotated row besequentially accessed from the frame buffer memory 170 in the same order(starting with rotated row and column address 0) for both clockwise andcounter-clockwise rotation.

The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteachings. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical application,to thereby enable others skilled in the art to best utilize theinvention and various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the claims appended hereto and theirequivalents.

We claim:
 1. A computer display system including a processor and adisplay system, the display system having a memory, said display systemcomprising: a display means for displaying image information to bearranged in a plurality of horizontal lines of pixel data; a framebuffer containing the for storing pixel data of an image information,the frame buffer being stored in the memory in a manner that data ofeach of the plurality of horizontal lines including pixel data for thedisplay means being stored in the memory resulting in the frame bufferoccupying in a contiguous block in the a memory, and , the frame bufferfurther being accessible by the a processor using a processor addressset of row and column addresses; a controller means for establishingfordetermining new row addresses of a controller address set as the columnaddresses of the processor address set, and establishing new columnaddress of the controller address set as the row addresses of theprocessor address set; the controller means being coupled to the displaymeans for transferring adapted to transfer the pixel data of the framebuffer to the a display means using the new controller address set, thecontroller means setting each of the new row addresses of the controlleraddress set as the difference between its current value and a maximumvalue of the new row addresses of the controller address set andproviding the pixel data of the frame buffer to the display means whilereferencing both the new row addresses and the new column addresses ofthe controller address set in an ascending order.
 2. The computerdisplay system of claim 1 wherein the maximum value of the new rowaddresses of the controller address set refers to the maximum rowaddress where the pixel data displayable on the display means are storedin the memory.
 3. The computer system of claim 1 wherein A displaysystem comprising: a frame buffer for storing pixel data of an image ina contiguous block in a memory, the frame buffer being accessible by aprocessor using a processor address set of row and column addresses; acontroller for determining new row addresses of a controller address setas the column addresses of the processor address set, and new columnaddresses of the controller address set as the row addresses of theprocessor address set; the controller adapted to transfer the pixel dataof the frame buffer to a display using the new controller address set,the controller means setssetting each of the new column addresses of thecontroller address set as the difference between its current value and amaximum value of the new column addresses of the controller address setand provides the pixel data of the frame buffer to the display meanswhile referencing both the new row addresses and the new columnaddresses of the controller address set in an ascending order.
 4. Thecomputer display system of claim 3 wherein the maximum value of the newcolumn address of the controller address set refers to the maximumcolumn address where the pixel data displayable on the display means arestored in the memory.
 5. A method for rotating images for a computersystem, the computer system including a processor, and a display system,the display system having and a memory, said method comprising the stepsof: displaying image information on display means arranged in aplurality of horizontal lines of pixel data; storing pixel data of animage in a frame buffer in the memory, the frame buffer containing theimage information , the frame buffer being stored in the memory in amanner such that data of each of the plurality of horizontal linesincluding pixel data for the display means are stored in the memoryresulting in the frame buffer occupying a contiguous block in the memoryand the frame buffer further being accessible by the processor using aprocessor address set of row and column addresses;establishingdetermining new row addresses of a controller address set asthe column addresses of the processor address set, and establishing newcolumn addresses of the controller address set as the row addresses ofthe processor address set; transferring the pixel data of from the framebuffer to the display means using the new controller address set, thetransferring step setting each of the new row addresses of thecontroller address set as the difference between its current value and amaximum value of the new row addresses of the controller address set andproviding the pixel data of from the frame buffer to the display meanswhile referencing both the subtracted-from-maximum new row addresses andthe new column addresses of the controller address set in an ascendingorder.
 6. The method of claim 5 wherein the maximum value of the new rowaddresses of the controller address set refers to the maximum rowaddress where the pixel data displayable on the display means are storedin the memory.
 7. The method of claim 5 wherein the transferring stepfurther includes A method for rotating images for a computer system, thecomputer system including a processor, a display and a memory, saidmethod comprising the steps of: storing pixel data of an image in aframe buffer, the frame buffer being stored in a contiguous block in thememory and the frame buffer being accessible by the processor using aprocessor address set of row and column addresses; determining new rowaddresses of a controller address set as the column addresses of theprocessor address set, and new column addresses of the controlleraddress set as the row addresses of the processor address set;transferring the pixel data from the frame buffer to the display usingthe new controller address set, the transferring step setting each ofthe new column addresses of the controller address set as the differencebetween its current value and a maximum value of the new columnaddresses of the controller address set and providing the pixel dataoffrom the frame buffer to the display means while referencing both thenew row addresses and the subtracted-from-maximum new column addressesof the control address set in an ascending order.
 8. The method of claim7 wherein the maximum value of the new column addresses of thecontroller address set refers to the maximum column address where thepixel data displayable on the display means are stored in the memory. 9.A graphics controller for rotating an image comprising: an interface toreceive a request for a pixel of the image from a processor, the pixelhaving a row address R and a column address C; an interface to retrievea new pixel instead of the requested pixel from a frame buffer, the newpixel having a row address X and a column address Y, wherein: a) inresponse to the image being rotated clockwise, X is column address C ofthe requested pixel, and Y is the difference between row address R ofthe requested pixel and a maximum row address; b) in response to theimage being rotated counterclockwise, X is the difference between columnaddress C of the requested pixel and a maximum column address, and Y isrow address R of the requested pixel; and an interface to output the newpixel to a display for display at row address X and column address Y.10. An apparatus for manipulating a processor's addressing of an imagefrom a frame buffer so that the image is rotated 90 degrees counterclockwise without requiring the processor to spend its cycles on addresstransformation operations, the apparatus comprising: a displayinterface; a frame buffer interface; a controller to establish new rowaddresses of a controller address set as the column addresses of aprocessor address set, and to establish new column addresses of thecontroller address set as the row addresses of the processor addressset; the controller being coupled to the display interface and the framebuffer interface to transfer the pixel data of a frame buffer to adisplay using the new controller address set, the controller to set eachof the new row addresses of the controller address set as the differencebetween its current value and the maximum value of the new row addressesof the controller address set and to provide pixel data of the framebuffer to the display while referencing both the new row addresses andthe new column addresses of the controller address set in ascendingorder.
 11. The frame buffer interface of claim 10 wherein the framebuffer for which the frame buffer interface is transferring pixel datais stored in a memory in a manner such that data of each of theplurality of horizontal lines including pixel data to be displayed onthe display is stored in the memory resulting in the frame bufferoccupying a contiguous block in the memory and the frame buffer isfurther accessible by a processor using a processor address set and rowand column addresses.
 12. An apparatus for manipulating a processor'saddressing of an image from a frame buffer so that the image is rotated90 degrees clockwise without requiring the processor to spend its cycleson address transformation operations, the apparatus comprising: adisplay interface; a frame buffer interface; a controller to establishnew row addresses of a controller address set as the column addresses ofa processor address set, and to establish new column addresses of thecontroller address set as the row addresses of the processor addressset; the controller being coupled to the display interface and the framebuffer interface to transfer the pixel data of a frame buffer to adisplay using the new controller address set, the controller to set eachof the new column addresses of the controller address set as thedifference between its current value and the maximum value of the newcolumn addresses of the controller address set and to provide pixel dataof the frame buffer to the display while referencing both the new rowaddresses and the new column addresses of the controller address set inascending order.
 13. The frame buffer interface of claim 12 wherein theframe buffer for which the frame buffer interface is transferring pixeldata is stored in a memory in a manner such that data of each of theplurality of horizontal lines including pixel data to be displayed onthe display is stored in the memory resulting in the frame bufferoccupying a contiguous block in the memory and the frame buffer isfurther accessible by a processor using a processor address set and rowand column addresses.
 14. A system for rotating an image comprising: aprocessor to request a pixel of the image, the pixel having a rowaddress R and a column address C; a graphics controller to retrieve anew pixel instead of the requested pixel from a frame buffer, the newpixel having a row address X and a column address Y, wherein: a) inresponse to the image being rotated clockwise, X is column address C ofthe requested pixel, and Y is the difference between row address R ofthe requested pixel and a maximum row address; b) in response to theimage being rotated counterclockwise, X is the difference between columnaddress C of the requested pixel and a maximum column address, and Y isrow address R of the requested pixel; and wherein the graphicscontroller instructs a display to display the new pixel at row address Xand column address Y.
 15. A method of rotating an image, the imagecomprising a plurality of pixels, each pixel having a row address R anda column address C, the method comprising: receiving a request for apixel of the image, the pixel having a row address R and a columnaddress C; providing a new pixel having a new row address X and a newcolumn address Y wherein: a) in response to the image being rotatedclockwise, X is column address C of the requested pixel, and Y is thedifference between row address R of the requested pixel and a maximumrow address; b) in response to the image being rotated counterclockwise,X is the difference between column address C of the requested pixel anda maximum column address, and Y is row address R of the requested pixel;and repeating the receiving and providing steps for each pixel of theimage.
 16. A method for rotating images 90 degrees counter clockwisecomprising the steps of: establishing new row addresses of a controlleraddress set as the column addresses for a processor address set, andestablishing new column addresses of the controller address set as therow addresses for the processor address set; and setting each of the newrow addresses of the controller address set as the difference betweenits current value and the maximum value of the new row addresses of thecontroller address set.
 17. A method for rotating images 90 degreesclockwise comprising the steps of: establishing new row addresses of acontroller address set as the column addresses for a processor addressset, and establishing new column addresses of the controller address setas the row addresses for the processor address set; and setting each ofthe new column addresses of the controller address set as the differencebetween its current value and the maximum value of the new columnaddresses of the controller address set.